Computer and System Architecture meetup
The Core Count Explosion: A Challenge for Hardware and Software
The computer industry is seeing a core count explosion, with systems featuring hundreds of cores being the new normal.
Designing hardware and software for such massively parallel systems is far from trivial.
This trend is driven by the need for ever-more powerful computing systems to meet the demands of applications such as artificial intelligence, machine learning, and scientific computing.
Join our new meetup series for us working in the field of computer and system architecture. This first meetup will take place on the 25th floor of Kista Science Tower.
Agenda:
17:00 Doors open
17:15 Welcome by Vasakronan and Kista Science City
17:30 Presentation: How to utilise lock-free programming for more scalable programs, Ola Liljedahl
18:00 Presentation: Hardware complexity and how it impacts software, Jonas Svennebring
18:30 Networking, food and drinks (at own expence)
19:00 Joint Q&A
21:00 Event closes
Abstracts
Programmers want to scale up performance using the increasing core and thread counts that modern computer technology provides. This objective is often hindered by legacy software architectures (e.g. single thread programs or multithreaded programs with primitive locking schemes). In this talk we will describe how you can utilise lock-free programming in order to create more scalable programs and what you need to know about the hardware to make those programs correct and high-performing.
The industry is now seeing a core count explosion with devices having hundreds of cores being the new norm. The complexity of such systems, both from a hardware design as well as software utilization, is far from trivial. This presentation will give some inside peek into the hardware complexity and how it impacts software as well as what features one can leverage to drive up multicore software efficiency.
Meet the speakers
Ola Liljedahl is a system architect at Arm where he currently works with software and hardware architectures for parallel and concurrent systems. He has coded for many computer architectures (6502, 68K, SPARC, PowerPC, MIPS, ARM 32- and 64-bit) over the years.
Jonas Svennebring is a Principal Engineer at Intel who works on performance optimization: software improvements for current generation hardware and driving hardware improvements for future CPUs, primarily in the memory subsystem. He has a background working with x86 as well as PPC and ARM.