Using the RISC-V ISA in Practice
Computer and Systems Architeture meetup #3
Join our new meetup series “Computer and Systems Architecture meetup”, for us working in the field of computer and system architecture.
Agenda
17:00 Doors open
17:15 Welcome
17:30 Presentation on RISC-V: The pains of growing an ISA by Björn Töpel, Rivos
18:00 Heterogeneous multi-ISA, multi-data-model, RISC-V Research Platform by, Björn Forsberg, RISE
18:30 Networking, food and drinks (at own expence)
19:00 Joint Q&A
21:00 Event closes
Registration
RISC-V: The pains of growing an ISA
Björn Töpel, Rivos
Björn Töpel is a Linux kernel engineer at Rivos. Björn enjoys long walks, micro-architecture discussions, open source firmware, and a good networking stack.
Abstract:
RISC-V is a royalty-free, open standard ISA, originated in academia, but has since gained a strong interest in the industry. The original base RISC-V ISA started out very simplistically, to be used by students to implement their own designs. Today RISC-V is aiming for the whole compute spectrum, ranging from MCUs to HPC.
This talk is a case-study of some of the early/current missing pieces in the ISA, what modern software (including OSs, JITs) rely on from an ISA, and the on-going process of filling those gaps. It will also touch on some of more peculiar design choices, and how they affect the evolution of the ISA, and software porting. Can you start out too simple?
Heterogeneous multi-ISA, multi-data-model, RISC-V Research Platform
Björn Forsberg, RISE
Björn Forsberg received his M.Sc. degree from Uppsala Universitet in 2015, and his Ph.D. degree from ETH Zürich in 2021, for his work on timing-predictable execution for heterogeneous embedded real-time systems based on compiler and software-centric techniques for real-time guarantees on modern high-end embedded hardware. His interests lie in new and enabling technology at the hardware and software boundary, and its impact on programmability, real-time, energy-efficiency, and performance.
Abstract:
This talk presents our experiences building the hardware/software stack for HEROv2, a RISC-V-based Heterogeneous Research Platform based on the PULP Project at ETH Zürich. Heterogeneous computers integrate general-purpose host processors with domain-specific accelerators to combine versatility with efficiency and performance. Using the open and extensible RISC-V the HEROv2 heterogeneous research platform targets FPGAs and consists of 32-bit RISC-V accelerator cluster(s) and an application-class 64-bit ARMv8 or RISC-V host CPU. Several standard and custom RISC-V ISA extensions are supported, starting from RV32IMA, including bit-manipulation, hardware loops, post-incrementing load/stores, and more (Xpulpv2, Xssr, Xfrep, Xsdma). HEROv2 allows to seamlessly share data between 64-bit hosts and 32-bit accelerators using open-source cores, on-chip network, a unified heterogeneous programming interface, and a mixed-data-model, mixed-ISA heterogeneous compiler based on LLVM. HEROv2 is presented in IEEE Transactions on Parallel and Distributed Systems, https://doi.org/10.1109/TPDS.2022.3189390.